1. Field of the Invention
This invention relates to a semiconductor memory device and more particularly to the improvement of a sense amplifier for a dynamic RAM.
2. Description of the Related Art
With the development of the integrated circuit technology, semiconductor memory devices, especially, dynamic RAMs (which are hereinafter referred to as DRAMs) have come to be widely used in the field of electronics. Since it has become possible to form the DRAM of large capacity, applications requiring a large storage capacity of image memories or the like have been developed, but in this field, it is necessary to continuously read out stored data at high speed. At the time of readout of memory data, the main factor controlling the readout time is the time for readout from the memory cell to the sense amplifier. Therefore, various attempts have been made to apparently eliminate the readout time. For example, there is provided a data latch DRAM having a latch circuit which is provided between the sense amplifier and the I/O buffer and in which a readout instruction is temporarily held for future usage.
FIG. 1 shows the main portion of the general construction of the data latch DRAM. The data latch DRAM has a data latch circuit provided in the next stage of the sense amplifier in the memory core section of a normal standard DRAM. That is, in FIG. 1, 110 denotes a DRAM cell array, 111 a row address buffer, 112 a row decoder, 113 a word line level generator, 114 a sense amplifier, 115 a transfer gate, 116 a data latch circuit, 117 a column address buffer, 118 a column decoder, 119 a column selection gate, 120 a data bus, 121 an input/output (I/O) buffer, 122 a transfer gate control signal (WW) buffer, 123 a row controller, 124 a column controller, and 125 an external I/O bus. Further, the DRAM includes a transfer gate selector 126 as a control circuit for the transfer gate and a driver and precharger circuit 127 for the sense amplifier 114.
In this case, if the DRAM cell array 110 has a structure of M rows.times.N columns, the data latch circuit 116 is formed to have N latch circuits capable of holding data of one row. The structure is similar to the structure in which a cache portion is constructed by a data latch circuit of one row.times.N columns in a Cache DRAM.
The readout operation of the DRAM with the above construction is performed as follows. At the time of readout, a row address strobe signal (BRAS) is activated and a row address signal is input in synchronism with activation of the BRAS signal. By activation of the BRAS signal, the row controller 123 is driven and a boosted word line potential is created in the word line level generator 113. The boosted word line potential is given as a power supply of the row decoder 112 and the potential is supplied to a word line (not shown) selected by the row decoder 112.
If the word line is thus activated, data is read out from DRAM cells corresponding to the selected word line and supplied to corresponding bit lines (not shown). Further, in response to the signal of the row controller 123, a sense amplifier control signal generated from the driver and precharger circuit 127 is activated, data of N columns on the same row supplied to the bit lines as described before is sensed and latched by the N sense amplifiers 114. After this, the transfer gate control signal WW is activated to turn ON the transfer gate 115 between the sense amplifier 114 and the data latch circuit 116 so as to permit data latched by the sense amplifier 114 to be transferred to the data latch circuit 116. Latch data of the data latch circuit 116 is supplied via the column selection gate 119 selected by a column address signal input decoded by the column decoder 118 and then output to the external data bus 125 via the data bus 120 and input/output buffer 121.
In the above operation, after the transfer gate 115 is turned OFF when data is transferred to the data latch circuit 116, the DRAM cell array 110 and sense amplifier 114 can be operated independently of the data latch circuit 116 and the succeeding stage circuits.
Based on the above fact, if a next row address signal is input while data on the previous row is transferred between the data latch circuit 116 and the external data bus and new data on the row corresponding to the new row address is read out from the cell array 110 to the sense amplifier 114 and latched therein, new data can be transferred from the sense amplifier 114 to the data latch circuit 116 by turning ON the transfer gate 115 again when transfer of latch data from the data latch circuit 116 to the external data bus is terminated.
As a result, the time (normally, 50 ns or more) necessary for reading out data corresponding to the row address input from the DRAM cell array 110 to the sense amplifier 114 can be eliminated when viewing the DRAM from the external data bus. That is, new data can be read out at high speed from the data latch circuit 116 again after a short period of time (for example, 10 ns or less) required for transferring data from the sense amplifier 114 to the data latch circuit 116 by turning ON the transfer gate 115.
The schematic flow of the data writing operation of the data latch DRAM is explained as follows. First, data is input from the external I/O bus 125 to the I/O buffer 121. Then, a column address strobe (BCAS) signal is input to the column controller 124 from the outside of the chip and a column address signal is input to the column decoder 118 via the column address buffer 117 in synchronism with the BCAS signal. A column gate 119 corresponding to a column address designated by the column decoder 118 is activated. Further, the data is input from the I/O buffer 121 to the data bus 120 in synchronism with the BCAS signal. Then, data input to the data bus 120 is written into the data latch circuit 116 connected to the activated column gate. The operation of writing data into the data latch circuit 116 is performed with the transfer gate 115 kept in the OFF state. The above operation is repeatedly performed while changing write data and input column address. The operation of writing data into the data latch circuit 116 is performed only for columns which require rewriting of data. Therefore, data are not always written into all of the N data latch circuits 116.
Next, if the operation of writing data of one row from the data bus into the data latch circuit 116 is completed, the transfer gates 115 only for the columns for which data writing has been performed are turned ON to permit data to be simultaneously transferred from the data latch circuit 116 to the sense amplifiers 114 and memory cells 110. The operation can be attained by activating the transfer gate only for the columns for which data writing has been performed.
In the column for which data writing has not been performed, the same operation as the refresh operation in the normal DRAM is performed and data held in the memory cell is amplified again. Then, the data are written into the memory cell again. The above operations construct the schematic flow of the data writing operation.
However, in the DRAM with data latch having a function of transferring data as described above, if the number of columns in which simultaneous data transfer is performed increases, there occurs a possibility that the sense amplifier is incorrectly operated to invert and destroy the data to be refreshed in the column in which data transfer is not performed. That is, if the transfer gates of the columns in which data are written are simultaneously turned ON, the current driving ability of the driver and precharger circuit 127 for supplying a signal for driving the sense amplifiers 114 becomes insufficient and the signal potential fluctuates, thereby causing a possibility that data of the sense amplifier in which data rewriting is not performed are destroyed. This is a problem of the DRAM with data latch to be solved.